With the increasing number of Internet devices, the emergence of IoT, 5G and the increased traffic between the devices, the IPv6 is complementing IPv4. As IPv6 is becoming the protocol of choice by the new technologies, in order to accommodate for the features demanded by these technologies it is necessary to have high speed and low latency between the connected nodes. This paper introduces a hardwired IPv6 FPGA node, which processes IPv6 packets and is focused on high-speed transmission. Although, the code is written VHDL, it is written in a way which enables the user to easily add new features and implement new extension headers. The implementation of this IPv6 header processor is done on a Virtex7 VC709 FPGA development board.
Google, IPv6 adoption in the Internet [Online]. Available: https://www.google.com/intl/en/ipv6/ statistics.html, 2021.
Ch. M. Kozierok, The TCP/IP Guide: A Comprehensive, Illustrated Internet Protocols Reference, 1st ed. CA: No Starch Press, 2005.
P. C. Lekkas, Network Processors _ Architectures, Protocols and Platforms (Telecom Engineering). McGraw-Hill Professional, 2003.
J. M. P. Cardoso and M. Hubner, Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, NY: Springer-Verlag, 2011.
Xilinx, VC709 Evaluation Board for the Virtex-7 FPGA, User guide, 2016.
G. Gibb, G. Varghese, M. Horowitz, and N. McKeown, “Design principles for packet parsers,” in Proc. of ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp. 13–24, 2013.
J. Kořenek, “Hardware acceleration in computer networks,” in Proc. of 16th International Symposium on Design and Diagnostics of Electronic Circuits Systems, 2013.
R. Giladi, Network Processors - Architecture, Programming and Implementation, Ben-Gurion University of the Negev and EZchip Technologies Ltd., 2008.
B. Wheeler, A New Era of Network Processing. LinleyGroup Bob Wheeler's White paper, 2013.
Intel, Intel® IXP2800 and IXP2850 network processors, Product Brief, 2005.
B. Doud, “Accelerating the data plane with the Tilemx manycore processor,” in Linley Data Center Conference, 2015.
Z. Bokai, Y. Chengye, and C. Zhonghe, “TCP/IP Offload Engine (TOE) for an SOC System” in Nios II Embedded Processor Design Contest-Outstanding Designs, 2005.
U. Langenbach, A. Berthe, B. Traskov, S. Weide, K. Hofmann, and P. Gregorius, “A 10 GbE TCP/IP Hardware Stack as part of a Protocol Acceleration Platform,” in Proc. of 3rd IEEE International Conference on Comsumer Electronics, 2013.
D. Sidler, G. Alonso, M. Blott, K. Karras, K. Vissers, and R. Carley, “Scalable 10 Gbps TCP/IP Stack Architecture forReconfigurable Hardware,” in Proc. of 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015.
Mind Chasers, Private Island: Open Source FPGA- Based Network Processor for Privacy, Security, IoT, and Control, White paper, 2020 [Online]. Available: https://mindchasers.com/education.
·
This work is licensed under a
Creative Commons Attribution-ShareAlike 4.0 International License
