Software for Explicitly Parallel Memory-Centric Processor Architect

Goce Dokoski, Danijela Efnusheva, Aristotel Tentov, Marija Kalendar

References:

1. C. Carvalho, „The Gap between Processor and Memory Speeds“,3rd Internal Conference on Computer Architecture (ICCA'02), Braga, 2002
2. Memory Performance of Xeon E5-2600 v2 (Ivy Bridge-EP) based Systems, White Paper, Fujitsu, 2013
3. Schlansker, M.S.; Rau, B.R., "EPIC: Explicitly Parallel Instruction Computing," Computer , vol.33, no.2, pp.37,45, Feb 2000
4. P. Sirisuk et. al. (Eds.): ARC 2010, LNCS 5992, pp. 400-405, Springer-Verlag, Berlin Heidelberg, 2010
5. Kiyoung Choi, „Reconfigurable Computing: Architectures, Tools and Applications“, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010
6. Wassal, A.G.; Sarhan, H.H.; ElSherief, A., „Novel 3D memorycentric NoC architecture for transaction-based SoC applications", Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International, pp.1,5, 24-26, April 2011
7. Yamin Li, Sanli Li, and Wanming Chu, „Memory Centric Interconnection Mechanism for Message Passing in Parallel Systems“, Third International Conference on Massively Parallel Computing Systems (MPCS98), Colorado Springs, Colorado, Apr. 6–9, 1998
8. ChunYi Su, Dong Li, Dimitrios S. Nikolopoulos, Kirk W. Cameron, Bronis R. de Supinski, Edgar A. Le´on, Model-Based, „Memory-Centric Performance and Power Optimization on NUMA Multiprocessors, Workload Characterization (IISWC)“, 2012 IEEE International Symposium on , vol., no., pp.164,173, 4-6 Nov. 2012
9. D. Li, B. de Supinski, M. Schulz, K. Cameron, and D. Nikolopoulos, „Hybrid MPI/OpenMP Power-Aware Computing“, in IEEE International Symposium on Parallel Distributed Processing, 2010
10. K. Singh, M. Curtis-Maury, S. A. McKee, F. Blagojevi´c, D. S. Nikolopoulos, B. R. de Supinski, and M. Schulz, „Comparing Scalability Prediction Strategies on an SMP of CMPs“, Proc. of the 16th international Euro-Par conference on Parallel processing, 2010.
11. Berić, A.; Van Meerbergen, J.; de Haan, G.; Sethuraman, R., „Memory-Centric Video Processing“, Circuits and Systems for Video Technology, IEEE Transactions on , vol.18, no.4, pp.439,452, April 2008
12. Ivan Lunteren, J., „Towards memory centric computing: a flexible address mapping scheme", Electrical and Computer Engineering, 1999 IEEE Canadian Conference on , vol.1, no., pp.385,390 vol.1, 9-12 May 1999
13. Burger, D.; Goodman, J.R., „Memory-centric architectures: why and perhaps what", Innovative Architecture for Future Generation High-Performance Processors and Systems, 1997 , vol., no., pp.92,, 22-24 Oct 1997
14. Bonatto, A.C.; Susin, A.A., „Memory subsystem architecture design for multimedia applications“, VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on , vol., no., pp.213,214, 5-7 Aug. 2013
15. Gwangsun Kim; Kim, J.; Jung Ho Ahn; Jaeha Kim, „Memory-centric system interconnect design with Hybrid Memory Cubes“, Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on , vol., no., pp.145,155, 7-11 Sept. 2013
16. David A. Patterson, John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)”, Paperback, Morgan Kaufmann Publishers, Oct 2013
17. Kenneth Vollmar, Pete Sanderson, “MARS: An Education-Oriented MIPS Assembly Language Simulator”, SIGCSE'06 Houston, USA, March 2006