Proceedings of International Conference on Applied Innovation in IT
2017/03/16, Volume 1, Issue 5, pp.33-41
FPGA Implementation of IP Packet Header Parsing Hardware
Danijela Efnusheva, Aristotel Tentov, Ana Cholakoska, Marija Kalendar
Abstract: The rapid expansion of Internet has caused enormous increase in number of users, servers, connections and demands for new applications, services, and protocols in the modern multi-gigabit computer networks. The technology advances have resulted with significant increase of network connection links capacities, especially with the support for fiber-optic communications, while on the other hand the networking router's hardware and software have experienced many difficulties to timely satisfy the novel imposed requirements for high throughput, bandwidth and speed, and low delays. Considering that most network processors spend a significant part of processor cycles to provide IP packet header field access by means of general-purpose processing, in this paper we propose a specialized IP header parsing hardware that is intended to provide much faster IP packet processing, by allowing direct access to non byte- or word-aligned fields found in IPv4/IPv6 packet headers. The proposed IP packet header parser is designed as a specialized hardware logic that is added to the memory where the IP packet headers are placed; and is described in VHDL and then implemented in Virtex7 VC709 Field Programmable Gate Array (FPGA) board. The simulation timing diagrams and FPGA synthesis (implementation) reports are discussed and analyzed in this paper.
Keywords: FPGA, Header Parser, IP Packet Processing, Multi-gigabit Networks, Network Processor
- Ahmadi, M., Wong, S., 2006. Network processors: challenges and trends. In 17th Annual Workshop on Circuits, Systems and Signal Processing.
- Wheeler, B., 2013. A new era of network processing. LinleyGroup Bob Wheeler's White paper.
- Lekkas, P. C., 2013. Network Processors: Architectures, Protocols and Platforms, McGraw-Hill Professional.
- Shorfuzzaman, M., Eskicioglu, R., Graham, P., 2004. Architectures for network processors: key features, evaluation, and trends, Communications in Computing, pp.141-146.
- Giladi, R., 2008. Network Processors - Architecture, Programming and Implementation, Ben-Gurion University of the Negev and EZchip Technologies Ltd.
- Naous, J., Gibb, G., Bolouki, S., McKeown, N., 2008. NetFPGA: reusable router architecture for experimental research, in Sigcomm Presto Workshop.
- Petracca, M., Birkea, R., Bianco, A., 2008. HERO: High speed enhanced routing operation in software routers NICs. in IEEE Telecommunication Networking Workshop on QoS in Multiservice IP Networks. Intel, 2005. Intel® IXP2800 and IXP2850 network processors, Product Brief.
- Doud, B., 2015. Accelerating the data plane with the Tilemx manycore processor, in Linley Data Center Conference. Xilinx, 2016. VC709 Evaluation Board for the Virtex-7 FPGA. User guide.
- Cardoso, J. M. P., Hubner, M., 2011. Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, Springer-Verlag.
- Gibb, G., Varghese, G., Horowitz, M., McKeown, N., 2013. Design principles for packet parsers. In Proc. of the 40 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp. 13–24.
- Kořenek, J., 2013. Hardware acceleration in computer networks. In 16th International Symposium on Design and Diagnostics of Electronic Circuits Systems.
- Hauger, S., Wild, T., Mutter, A., 2009. Packet processing at 100 Gbps and beyond—challenges and perspectives. In 15th International Conference on
- High Performance Switching and Routing. Gupta, P., Lin, S., McKeown, N., 1998. Routing lookups in hardware at memory access speeds. In IEEE Infocom’98, pp. 1240–1247.
- Eatherton, W., Varghese, G., Dittia, Z., 2004. Tree bitmap: hardware/software IP lookups with incremental updates. In Sigcomm Computer Communication Review, vol. 34, no. 2.
- Kekely, L., Puš, V., Kořenek, J., 2014. Software Defined Monitoring of application protocols. In IEEE Conference on Computer Communications, pp. 1725–1733.
- Bolla, R., Bruschi, R., Lombardo, C., Podda, F., 2014. OpenFlow in the Small: A Flexible and Efficient Network Acceleration Framework for Multi-Core System. In IEEE Transactions on Network and Service Management, pp. 390-404.
- Puš, V., Kekely, L., Kořenek, J., 2014. Design methodology of configurable high performance packet parser for FPGA. In 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems, pp. 189–194.
- Attig, M., Brebner, G., 2011. 400 Gb/s Programmable Packet Parsing on a Single FPGA. In Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems, pp. 12-23.
- Brebner, G., Jiang, W., 2014. High-Speed Packet Processing using Reconfigurable Computing. In IEEE Micro, vol. 34, no. 1, pp. 8– 18.
- Patterson, D., A., Hennessy, J., L., 2014. Computer organization and design: the hardware/software interface, Elsevier. 5th ed.