Proceedings of International Conference on Applied Innovation in IT
2014/03/27, Volume 1, Issue 2, pp.29-35

Implementation of Multi-Core Processor Based on PLASMA (most MIPS I) IP Core


Bojan Gruevski, Aristotel Tentov, Marija Kalendar


Abstract: Multi-core processors is a design philosophy that has become mainstream in scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices has permitted complex logic systems to be implemented on a single programmable device. By using VHDL here we present an implementation of one multi-core processor by using the PLASMA IP core based on the (most) MIPS I ISA and give an overview of the processor architecture and share the execution results.

Keywords: FPGA, multi-core processor, MIPS, PLASMA, core, implementation, architecture, design

DOI: 10.13142/kt10002.05

Download: PDF

References:

  1. M. J. Flynn, “Computer Architecture: Pipelined and Parallel Processor Design,”. Jones & Bartlett Learning, Sudbury, Massachusetts, 1995.
  2. J. L. Hennessy, D. A. Patterson, “Computer Architecture - A Quantitative Approach,” 4th Edition. Morgan Kaufman Publishers, Burlington, Massachusetts, 2007.
  3. A. S. Tanenbaum, “Modern Operating Systems,” 2nd edition. Prentice Hall, Upper Saddle River, New Jersey, 2002.
  4. Plasma – most MIPS I (TM) opcodes: Overview [Online]. Available: http://opencores.org/project,plasma,overview, (October, 2013)
  5. MIPS M51xx Warrior-M class CPU Core [Online]. Available: http://www.mips.com/, (November, 2013)
  6. Xilinx [Online]. Available: http://www.xilinx.com/, (October, 2013)
  7. Altera [Online]. Available: http://www.altera.com/, (October, 2013)
  8. David A. Patterson, John L. Hennessy, “Computer Organization and Design - The Hardware/Software Interface”, 3rd Edition. Morgan Kaufman Publishers, Burlington, Massachusetts, 2005.
  9. J. M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic “Digital Integrated Circuits - A Design Perspective”, 2nd Edition, Prentice-Hall, Upper Saddle River, New Jersey, 2002.
  10. D. Silva, K. Stangherlin, L. Bolzani, F. Vargas, “A Hardware-Based Approach to Improve the Reliability of RTOS-Based Embedded Systems,” IEEE Computer Society, 2011, p. 209.
  11. J. Tarrillo, L. Bolzani, and F. Vargas, “A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems,” Digital System Design, Architectures, Methods and Tools, 2009, pp. 341 – 347.

    Home

    PARTICIPATION

       - Call for Papers!!!
       - Paper Submission
       - Important Dates
       - Committee
       - Guest registration


    PROCEEDINGS

       - Issue 1 (ICAIIT 2013)
       - Issue 2 (ICAIIT 2014)
       - Issue 3 (ICAIIT 2015)
       - Issue 4 (ICAIIT 2016)
       - Issue 5 (ICAIIT 2017)

    ETHICS IN PUBLICATIONS

    ACCOMODATION

    CONTACT US

 


           ISSN 2199-8876
           Copyright © 2013-2017 Leonid Mylnikov. All rights reserved.