Proceedings of International Conference on Applied Innovation in IT
2019/03/06, Volume 7, Issue 1, pp.23-29
Hardware Implementation of IP Packet Filtering in FPGA
Ana Cholakoska, Danijela Efnusheva, Marija Kalendar
Abstract: In the present rapid expansion of the number of computers and devices connected to the Internet, one of the top three issues that need to be addressed is the network security. The greater the number of connected users and devices, the attempts to invade privacy and data of connected users becomes more and more tempting to hostile users. Thus, network intrusion detection systems become more and more necessary and present in any network enabling Internet connections. This paper addresses the network security issues by implementing NIDS style hardware implementation for filtering network packets intended for faster packet processing and filtering. The hardware is based on several NIDS rules that can be programmed in the system's memory, thus enabling modularity and flexibility. The designed hardware modules are described in VHDL and implemented in a Virtex7 VC709 FPGA board. The results are discussed and analyzed in the paper and are presenting good foundation for further improvement.
Keywords: FPGA, IP Header Fields Extracting, IP Packet Filtering, Network IDS Systems
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